The present invention relates to a computer system, and more particularly to a computer system with a cache memory.
A main memory of a computer system stores large quantities of required data. A data processor gives an address signal to the main memory to access and use the data stored therein.
It is highly possible that the data requested by the data processor is then often repeatedly used. However, the data is read out from the main memory at each request at low speed. The repeated access reduces the processing speed of the entire system.
To address this circumstance, a system architecture has been popularized which temporarily stores the data once used by the data processor in a buffer memory, called the cache memory. Data to be accessed repetitively can be stored in the cache. The cache memory operates at high speed and has relatively small capacity so that, when again accessing the same data, the data is read out from the cache memory, thereby improving processing speed.
In the drawing, reference numeral 1 designates a data processor, which outputs an address signal through an address bus 4a to access data. Data processor 1 reads data received on a data bus 5a from a cache memory 2 to be discussed below, or a main memory 3. Data processor 1 outputs a non-cachable signal through a non-cachable signal line 6. The non-cachable signal is output from the data processor 1 to the cache memory when accessing data not held by cache memory 2.
Cache memory 2 is connected to data processor 1 through the aforesaid address bus 4a, data bus 5a and non-cachable signal line 6. Cache memory 2 outputs through an address bus 4b the address signal output from the data processor 1 so as to read in the data through a data bus 5b.
The main memory 3 is connected with the cache memory 2 through the address bus 4a and data bus 5b. The main memory 3 is of relatively larger capacity than cache memory 2, but operates at low speed. On the other hand, cache memory 2 is of relatively smaller capacity than main memory 3, but operates at high speed.
In operation, data processor 1 outputs via address bus 4a, an address signal indicating the address of data to be accessed at the main memory 3. This address signal is given to cache memory 2. When the address data is held in cache memory 2 (hereinafter called "cache hit"), cache memory 2 immediately outputs the data to the data processor 1 through the data processor 1 through the data bus 5a.
When the data to be accessed by the data processor 1 is not held in cache memory 2 (hereinafter called "cache miss"), cache memory 2 outputs, through address bus 4a, the address signal given from data processor 1 so as to access the data. Main memory 3 then outputs to data bus 5b the data corresponding to the address signal given from the cache memory 2. Cache memory 2 stores and holds therein the data output from main memory 3 (hereinafter called "caching") and gives the data to data processor 1 through data bus 5a.
In the case where data, in an I/O area or the like, is not desired to be held in cache memory 2, data processor 1 outputs the address to be accessed on address bus 4a and outputs the non-cachable signal on non-cachable signal line 6. Cache memory 2 outputs the address to address bus 4b to access to the I/O area of main memory 3 without deciding whether or not the data is to be accessed is cached. Cache Memory 2 also outputs the read-out data to data bus 5a without holding it, thereby giving the data to data processor.
FIG. 2 is a block diagram of the cache memory 2 of detailed structure, which is of 2-way set associative system, addresses of 7 bits, and 4-entries. In FIG. 2, reference numeral 11 designates an address which is output from the data processor 1 to address bus 4a as above-mentioned. Address 11 comprises an address tag 12 of 4 bits, an entry address 13 of 2 bits and a byte address 14 of 1 bit.
The contents of address tag 12 are given to comparators 19 (19a and 19b). The entry address 13 is given to a decoder 15, and the byte address 14 is given to byte selectors 20 (20a and 20b).
The decoder 15 decodes the entry address 13 of the address 11. The decoded result by the decoder 15 is given to the tag memories 16 (16a and 16b) and data memories 18 (18a and 18b).
The tag memories 16 (16a and 16b) store therein the address tag 12 of address 11. The stored content of tag memory 16a is output to comparator 19a. The stored content of tag memory 16b is output to comparator 19b.
Data memories 18 (18a and 18b) store therein two bytes of data indicated by the address stored in the tag memories 15. The stored content of data memory 18a is output to the byte selector 20a, and the contents of data memory 18b is output to the byte selector 20b.
Reference numerals 17 (17a and 17b) designate valid bits for indicating whether or not the stored contents of data memories 18 (18a and 18b) are effective. The content of valid bit 17a is output to the comparator 19a, and that of valid bit 17b to the comparator 19b.
The comparators 19 (19a and 19b) decide whether or not the address tag 12 and tag memories 16 (16a and 16b) are coincident of the content with each other. The decision result is given as hit signals 21 (21a and 21b) to a way selector 22.
The byte selectors 20 (20a and 20b) select byte data of data memories 18 (18a and 18b) in accordance with the content of byte address 14.
Subscripts "a" and "b" to reference numerals 16 through 21 show that they correspond to the two ways respectively.
The way selector 22 selects an output of byte selectors 20 by the hit signal 21, the selection result being output as a data output 23.
Cache memory 2 thus operates as described in the following paragraphs.
Upon receiving address 11 from data processor 1, entry address 13 of address 11 is decoded by decoder 15. The content of tag memory 16 of each way indicated by the above decoded result is given to comparators 19. The contents of data memories 18 are given to byte selectors 20, and byte data selected thereby is sent to way selector 22. The content of the selected tag memory 16 together with the contents of valid bits 17 of the selected tag memory 16 are judged by the comparators 19 as to whether or not the same coincides with address tag 12. When the coincident way exists, way selector 22 outputs data of that way as a data output 23. However, when the memory contents and address 12 compared by comparators 19, are not coincident, data accessing is executed not from cache memory 2 but from main memory 3. The corresponding data is read out from main memory 3 and given to data processor 1. The corresponding data is also stored in data memories 18 of cache memory 2.
In a conventional computer system having the above-mentioned construction, the capacity of the cache memory can only increase by increasing the size and capacity of the cache memory itself. Entire computer systems are generally composed of a single LSI chip. Therefore, increasing the capacity of cache memory requires fundamental redesign of the chip. Thus, the capacity of cache memory is not easily increased.